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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">GICR_INMIR0, Non-maskable Interrupt Register 0</h1><p>The GICR_INMIR0 characteristics are:</p><h2>Purpose</h2>
        <p>Controls whether the corresponding SGI or PPI has the non-maskable property.</p>
      <h2>Configuration</h2><p>This register is present only when FEAT_GICv3_NMI is implemented. Otherwise, direct accesses to GICR_INMIR0 are <span class="arm-defined-word">RES0</span>.</p>
        <p>When <a href="ext-gicd_typer.html">GICD_TYPER</a>.NMI is 0, this register is <span class="arm-defined-word">RES0</span>.</p>

      
        <p>A copy of this register is provided for each Redistributor.</p>
      <h2>Attributes</h2>
        <p>GICR_INMIR0 is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="1"><a href="#fieldset_0-31_0">nmi31</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">nmi30</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">nmi29</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">nmi28</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">nmi27</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">nmi26</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">nmi25</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">nmi24</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">nmi23</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">nmi22</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">nmi21</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">nmi20</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">nmi19</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">nmi18</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">nmi17</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">nmi16</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">nmi15</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">nmi14</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">nmi13</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">nmi12</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">nmi11</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">nmi10</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">nmi9</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">nmi8</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">nmi7</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">nmi6</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">nmi5</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">nmi4</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">nmi3</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">nmi2</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">nmi1</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">nmi0</a></td></tr></tbody></table><h4 id="fieldset_0-31_0">nmi&lt;x&gt;, bit [x], for x = 31 to 0</h4><div class="field">
      <p>Non-maskable property.</p>
    <table class="valuetable"><tr><th>nmi&lt;x&gt;</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Interrupt does not have the non-maskable property.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Interrupt has the non-maskable property.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a GIC reset, 
      this field resets
       to <span class="binarynumber">0</span>.
</li></ul></div><div class="text_after_fields"><p>If affinity routing is disabled for the Security state of an interrupt, the bit is <span class="arm-defined-word">RES0</span>.</p>
<p>This bit is <span class="arm-defined-word">RES0</span> when the corresponding interrupt is configured as Group 0.</p></div><h2>Accessing GICR_INMIR0</h2>
        <p>Bits corresponding to unimplemented interrupts are RAZ/WI.</p>

      
        <p>When <a href="ext-gicd_ctlr.html">GICD_CTLR</a>.DS==0, bits corresponding to Group 0 and Secure Group 1 interrupts are RAZ/WI to Non-secure accesses.</p>

      
        <div class="note"><span class="note-header">Note</span><p>Implementations must ensure that an interrupt that is pending at the time of the write uses either the old value or the new value and must ensure that the interrupt is neither lost nor handled more than one time. The effect of the change must be visible in finite time.</p></div>
      <h4>GICR_INMIR0 can be accessed through the memory-mapped interfaces:</h4><table class="info"><tr><th>Component</th><th>Frame</th><th>Offset</th><th>Instance</th></tr><tr><td>GIC Redistributor</td><td>SGI_base</td><td><span class="hexnumber">0x0F80</span></td><td>GICR_INMIR0</td></tr></table><p>Accesses on this interface are <span class="access_level">RW</span>.</p><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:07; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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